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From: mash@mips.com (John Mashey)
Newsgroups: comp.arch
Subject: Re: Low End NeXTs (was Re: Desktop publishing)
Message-ID: <1872@spim.mips.COM>
Date: 4 Apr 91 04:21:34 GMT
References: <34936@athertn.Atherton.COM> <27fa3350.6bc2@petunia.CalPoly.EDU> <1991Apr03.232400.1560@kithrup.COM>
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In article <1991Apr03.232400.1560@kithrup.COM> sef@kithrup.COM (Sean Eric Fagan) writes:
>I would suggest that this thread continue in comp.arch, which is more suited
>to it.

>In article <27fa3350.6bc2@petunia.CalPoly.EDU> araftis@polyslo.CalPoly.EDU (Alex Raftis) writes:

>>On the other hand, look at the 68040. It executes instructions at around
>>1.3 cycles per instuction. 
It is very difficult to verify such a number, or make reasonable
comparisons without being the architects.  As noted in earlier posting,
if you try to use SPECint/Mhz, you find that the best CISC micros,
with 128KB external caches, get about .5 - .53 (@ 25MHz), i.e.,
12.9 - 13.3 for 68040 & 486.  RISCs get as much as .75-.80
(MIPS, IBM, HP PA). Using that as inverse of CPI, one gets
cycles/SPEcint of 1.88 (at best) for the CISCs, and 1.25 for RISCs.
Of course, FP is a more variable story; the RISCs have, at minimum
at least some additional advantage, more than integer,
and often a lot more.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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