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From: ftower@ncar.ucar.EDU (Francis Tower)
Newsgroups: comp.lang.fortran
Subject: Re: Cray memory stride (was Re: vectorization question reposed)
Message-ID: <10856@ncar.ucar.edu>
Date: 1 Apr 91 16:30:06 GMT
References: <1991Mar30.142903.5225@ariel.unm.edu> <27758@uflorida.cis.ufl.EDU> <1512@sunc.osc.edu>
Sender: news@ncar.ucar.edu
Reply-To: ftower@ncar.ucar.EDU (Francis Tower)
Organization: Climate and Global Dynamics Division, NCAR
Lines: 40

John,

I was out to lunch on my memory stride comments.  David Heisterberg
(a nice german name) was correct.  It is subsection conflicts which 
have precedence over the bank conflicts for a single CPU.  The memory
stride and relative performances for the subsections are:

  Mod(STRIDE, 32)          rel. Performance

       0                      1/5
     1 - 7                     1
       8                      4/5
     9 - 15                    1
       16                     2/5
     17- 23                    1
       24                     4/5
     25-31                     1


   There are 3 types of memory conflicts:
     Section -- two or more ports in the same CPU want to access the
                same memory section.

     Subsection -- a port in the same CPU wants to access the same
                subsection referenced by another port.  Wait time is
                1 to 4 clocks.

     Bank -- any port from any CPU wants to access a bank (at the
             same time or subsequently).  Wait time is 1 to 5 clocks.
             Cray breaks this into two cases 'Simultaneous Bank' and
             'Bank Busy'.

Today, It's Racquet Ball!

Francis G Tower
Software QA
NCAR/CGD/ICS

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