Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!elroy.jpl.nasa.gov!swrinde!cs.utexas.edu!wuarchive!cec2!news From: jab0396@cec2.wustl.edu (John A. Breen) Newsgroups: comp.lang.vhdl Subject: Re: High level modelling in VHDL Message-ID: <1991Mar29.141754.14579@cec1.wustl.edu> Date: 29 Mar 91 14:17:54 GMT References: <91087.160350WOOA@QUCDN.QueensU.CA> Organization: Washington University, St. Louis MO Lines: 32 In article <91087.160350WOOA@QUCDN.QueensU.CA> writes: >Eric Jenn (jenn@laas.laas.fr) writes: > >> So the real question is : >> "is VHDL sufficiently powerful to be a hardware description language AND a >> system level simulation language ?" > >Jukka Lahki (jukka@tk4.oulu.fi) replied: > >> In my experience, it is ... you definitely need a graphical method ... > >[...] I would say from my work that VHDL is not >powerful enough to simulate high level modelling paradigms. > >I would be interested to know if anyone else is working on high level >modelling in VHDL. I've looked at this problem quite a bit myself. My biggest problem with using VHDL for high-level modeling is that the only communication path between processes is signals. As Mr. Lahki said, you can usually do it if you want to write all of the necessary code, but it's not fun. I would really like to see a high-level communication "object" in VHDL that would take care of all of the overhead that signals require. BTW, I believe I-Logix (sp?) has a tool to translate statecharts into VHDL. ----- John A. Breen | johnb@hobbes.mdc.com McDonnell Douglas Missile Systems Co. | jab0396@cec1.wustl.edu (forwarded ^) Tel: (314)234-4341