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From: vahid@vesta.ics.uci.edu (Frank Vahid)
Newsgroups: comp.lang.vhdl
Subject: Re: High level modelling in VHDL
Message-ID: <27F3B6FD.16763@ics.uci.edu>
Date: 29 Mar 91 21:51:57 GMT
References: <91087.160350WOOA@QUCDN.QueensU.CA>
Organization: UC Irvine Department of ICS
Lines: 19
Nntp-Posting-Host: vesta.ics.uci.edu

>I agree with Mr. Lahti in that a graphical interface is the preferred
>entry mode into VHDL.  But I would say from my work that VHDL is not
>powerful enough to simulate high level modelling paradigms.  I have
>tried to translate Petri nets and statecharts (developed by David Harel)
>into VHDL and found it too restrictive.  For instance, Petri nets are
>intrinsically non-deterministic and VHDL cannot simulate random ordering
>of processes.  VHDL also lacks complete process control need to stop, suspend,
>restart processes, a feature required by statecharts.

I'm not exactly sure of the problems encountered with your StateCharts
translation, but I would refer you to a paper entitled "Translating
System Specifications to VHDL" which appeared in this year's EDAC
Procededings (European Design Automation Conference), dealing with
translating languages which are variants of StateCharts to VHDL.  I think
that a solution to the issue of complete process control is shown. Many
other translation problems and solutions are also covered.


Frank  (vahid@ics.uci.edu)