Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!bu.edu!inmet!davidb
From: davidb@inmet.inmet.com
Newsgroups: comp.lang.vhdl
Subject: Re: High level modelling in VHDL
Message-ID: <381900013@inmet>
Date: 2 Apr 91 15:17:00 GMT
References: <141754@<1991Mar29>
Lines: 30
Nf-ID: #R:<1991Mar29:141754:inmet:381900013:000:1513
Nf-From: inmet.inmet.com!davidb    Apr  2 10:17:00 1991


/* Written  4:03 pm  Mar 28, 1991 by WOOA@QUCDN.QueensU.CA */

>For instance, Petri nets are intrinsically non-deterministic and VHDL
>cannot simulate random ordering of processes.  VHDL also lacks
>complete process control need to stop, suspend, restart processes, a
>feature required by statecharts.

Work at the University of Virginia (under Dr. Jim Ayler) on what they
call "Uninterpreted Modeling" tends to negate this conclusion.  Their
models are similar to Petri nets, although they have some different
features.  Stoping, suspending, and restarting processes is a matter
of having VHDL processes include the logic to wait and re-start as
necessary, using the appropriate wait statements.

I think the question here is not one of intrinsic power --- after all,
VHDL can simulate a Turing machine.  The question is one of
convenience and ease of use.  In many ways VHDL is constructed to
facilitate design in the conceptual frame of hardware design.  The
question is how much one must "bend" his thinking to accomodate
systems description to the conceptual frame of VHDL.  I have heard
varying opinions on this question.  The most successful attempts have
been similar to the efforts at Virginia --- put a lot of effort into
some high level systems models, then concentrate on using the
structural aspects of VHDL to instantiate these models; this is a lot
closer to the intuitive systems models (especially with a graphics
front end, much as I hate the things).

						Dave Barton
						barton@i2wash.com