Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!cs.utexas.edu!titan!steve From: steve@titan.tsd.arlut.utexas.edu (Steve Glicker) Newsgroups: comp.lang.vhdl Subject: Re: High level modelling in VHDL Message-ID: Date: 3 Apr 91 20:52:11 GMT References: <141754@<1991Mar29> <381900013@inmet> Sender: news@titan.tsd.arlut.utexas.edu Organization: Applied Research Labs, The University of Texas at Austin Lines: 32 In-reply-to: davidb@inmet.inmet.com's message of 2 Apr 91 15:17:00 GMT I am sorry I missed the first part of this discussion because I am very interested in how VHDL might be used to describe high level-system designs. I did see the posting shown below. I would appreciate any references to papers or other leads on work related this topic. If there is interest I will post a summary of my findings. vahid@vesta.ics.uci.edu (Frank Vahid) writes: > I'm not exactly sure of the problems encountered with your StateCharts > translation, but I would refer you to a paper entitled "Translating > System Specifications to VHDL" which appeared in this year's EDAC > Procededings (European Design Automation Conference), dealing with > translating languages which are variants of StateCharts to VHDL. In article <381900013@inmet> davidb@inmet.inmet.com writes: > Work at the University of Virginia (under Dr. Jim Ayler) on what they > call "Uninterpreted Modeling" tends to ... [convey a position on systems modeling with VHDL] > ... The most successful attempts have > been similar to the efforts at Virginia --- put a lot of effort into > some high level systems models, then concentrate on using the > structural aspects of VHDL to instantiate these models; this is a lot > closer to the intuitive systems models ... -- Steve Glicker Applied Research Laboratories The University of Texas at Austin (steve@titan.tsd.arlut.utexas.edu)