Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!elroy.jpl.nasa.gov!decwrl!ucbvax!hplabs!hpcc05!hpsciz!stout
From: stout@hpsciz.sc.hp.com (Tim Stoutamore)
Newsgroups: comp.sys.apple2
Subject: Re: Re- AE RumorsMessage-ID- <1
Message-ID: <9090002@hpsciz.sc.hp.com>
Date: 29 Mar 91 21:10:24 GMT
References: <12998@ucrmath.ucr.edu>
Organization: Hewlett-Packard, Santa Clara, CA
Lines: 17

Randy Hyde writes:
>The 65xxx family has always used a two-phase clock and a high performance
>bus interface.  X Mhz on a 65xxx is comparable to 2X Mhz on most other
>processors (at least, in terms of memory access times).  A 25Mhz 65c816
>(on the bus anyway) is comparable to a 80386 running at 50Mhz (please, no
>flames or jumping for joy, the performance of the two is not the same for
>reasons I'll soon get in to).  Indeed, the two-phase clock is assymmetrical,
>so memory access time is even faster than this.

You are mixing apples and oranges.  It is not correct to say the two-phase
clock is assymmetrical unless you are talking about a particular system.  You
are talking about a microprocessor that can be designed into a multitude of
systems.  The system provides the clock, not the microprocessor.  In addition,
although I am not familiar with the Apple II, the 65xxx systems that I am
familiar with do use a symmetrical clock.  I used to work at Rockwell as an
applications engineer.  All the apps notes and applications that I saw there,
and the systems that I have designed, use a symmetrical clock.