Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!elroy.jpl.nasa.gov!ames!uhccux!uhunix1.uhcc.Hawaii.Edu!kiki From: kiki@uhunix1.uhcc.Hawaii.Edu Newsgroups: comp.sys.atari.st Subject: Atari cpu evolution Keywords: Motorola 68040 Message-ID: <12229@uhccux.uhcc.Hawaii.Edu> Date: 1 Apr 91 07:31:56 GMT Sender: news@uhccux.uhcc.Hawaii.Edu Organization: University of Hawaii Lines: 81 [someone speculates about evolution of Atari TT models with Motorola 68040 cpu] I guess it would be safe to assume that Atari is considering the '040 cpu for their next generation along the TT product line. But the microprocessor spec- trum has shifted from the dominance of the 80x86 and 68000 families from Intel and Motorola. One alternative is mentioned by the author of the following art- icle. And although he seems to disdain the specifications of the chip, I think it might be of significance and worthy of serious consideration. -------------------------[start of article]------------------------------------ >From: neideck@kaputt.enet.dec.com (Burkhard Neidecker-Lutz) Subject: PgC 7600 (was Re: Second-generation RISC) Organization: CEC Karlsruhe I'm typing what I've read in a local computer magazine here in Germany. The magazine isn't exactly known for overwhelming accuracy, so beware. Summary: I'm underwhelmed. Done by small British company called PgC, Ltd. (Yawn). Funded by Clive Sinclair (Oha !). RISC machine with a couple of onboard systems to make cheap machine implementation possible. The components: - Timer (connects to IFU) - Serial control unit (SCU) connects to IFU and external world - Instruction Fetch Unit (IFU) connects to ECU and external world - Execution Control Unit (ECU) connects to a ROM and QCache - CPU 6ns self clocking design coupled with 160 Byte of 3ns RAM - Memory Controller (MCU) connects to CPU, QCache and external world. The ROM can be used to store emulation code for CISC instructions ( I assume this is similar to what Clipper has). Price abotu 600 Deutsche Mark ( 400 $) External RAM interface: Separate Data and Address, 160 MByte/sec. bandwidth. Qcache is 32 instructions deep. Integrated support for dual-ported SRAMS in MCU, claim that this enables multiprocessor systems. At last a (buggy) table showing planned routes into the future: Name When Price Technology MIPS PgC7600 1/91 400 $ Bipolar 200 PgC7610 2/92 40 $ CMOS 80 PgC7620 1/93 100 $ Bipolar 250 PgC7700 2/93 400 $ CMOS 1000 PgC7710 4/93 200 $ Bipolar 2000 If you ask me: Too little, too late, no serious performance, no software. Forget it. Burkhard Neidecker-Lutz, CEC Karlsruhe ------------------------------[end of article]--------------------------------- If the PgC series has the capability of adaptable microcode and CISC emulation, then it would merit consideration by Atari as an alternative to the Motorola 68000 line. At the very least, it would offer Atari a little leverage against Motorola's monopoly of the '030 and '040 market. At best, Atari would have a computer that could run 80x86/68000/6502 etc. binary code, by loading the proper microcode. Although the German author perceives the PgC chips as unviable, there are other firms that are ready to market similar chips (NexGen, San Jose, CA) that have CISC emulation and multiprocessing capabilities. The pricing and performance seem to be exceptional to me and are some of the qualities associated with Clive Sinclair (and perhaps Atari), so that a Timex 200000K could soon be in our hands? The British press probably has reported on the PgC chips more extensively and I wonder if anyone there could make corrections, additions and their perspect- ive on the preceding information? Thanks, Jack