Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!hp-pcd!hpfcso!hpfcmgw!jeff
From: jeff@hpfcmgw.HP.COM (Jeff Taylor)
Newsgroups: comp.sys.hp
Subject: s700 questions answered
Message-ID: <17780016@hpfcmgw.HP.COM>
Date: 2 Apr 91 20:04:13 GMT
Organization: HP Fort Collins, CO
Lines: 32


>> Cache: 128 kB instr/256 kB data (720, 730), 256 kB instr/256 kB data.

> Are these external caches (sound too big to be on chip)?  How much
> (if any) delay does a cache access cost?  

IEEE Spectrum (April, 1991) has an article on page 58 entitled "How
ICs impact workstations" which describes "the design process employed
by a group of HP workstation designers in creating a prototype for a high
performance low-cost workstation ..."  The article states:

      The memory I/O controller was designed
    to work with 256K-by-4, 1M-by-4, or 4M-
    by-4-bit DRAMS. The timing and polarity of
    the control signals can be programmed at
    boot up time.  This allows different speeds
    of DRAMs and different loading (number of
    arrays) to be optimized. With 80-ns DRAMs,
    the memory system will fire first data back
    to the CPU 115 ns after the address has been
    received from the CPU. Subsequent data will
    be supplied at every 66-MHz clock edge.
      The memory controller is optimized to
    service cache misses to the CPU. The cache
    line size is 32 bytes...

For lots of additional information, see the article. Any typos are
mnie. I think that answers this question, but hey, I'm just a
software guy.

Hope this helps,
Jeff Taylor