Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!hp-pcd!hpfcso!cag
From: cag@hpfcso.FC.HP.COM (Craig Gleason)
Newsgroups: comp.sys.hp
Subject: Re: s700 questions answered
Message-ID: <7370357@hpfcso.FC.HP.COM>
Date: 3 Apr 91 20:30:03 GMT
References: <17780016@hpfcmgw.HP.COM>
Organization: Hewlett-Packard, Fort Collins, CO, USA
Lines: 31

>>> Cache: 128 kB instr/256 kB data (720, 730), 256 kB instr/256 kB data.
>
>> Are these external caches (sound too big to be on chip)?  How much
>> (if any) delay does a cache access cost?  
>
Yes, the caches are external.  They're implemented with industry standard
asynchronous SRAM's (15ns for the 50MHz systems, 12ns for the 66MHz ones).

Jeff's answer covers cache miss cases.  I might add that on both D-cache
and I-cache misses, execution proceeds when the missing data is supplied
("streaming") and continues to do so as the miss is processed.

On cache hits, the following applies:

Loads take only a single state on the cache address and data buses (we
issue a new load address each state).  The same goes for instruction 
fetches on the I-cache.  If the instruction following the load uses the
load data as an operand, there is a one state penalty (load-use).

Stores take three states on the D-cache.  This is a read-modify-write
operation combining a one state read with a two state write.  If the two
instructions following the store do not use the D-cache, the store will
appear to take only one state.  Otherwise, there will be one or two 
penalty states depending on when the next D-cache access is.  

eg.  store-load-add  :  two penalty states
     store-add-load  :  one penalty state
     store-add-add   :  no penalty

Craig Gleason
Hewlett-Packard