Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!elroy.jpl.nasa.gov!ncar!gatech!psuvax1!news From: melling@cs.psu.edu (Michael D Mellinger) Newsgroups: comp.sys.next Subject: Re: RISC vs. CISC -- SPECmarks Message-ID: Date: 4 Apr 91 00:49:49 GMT References: <14483@life.ai.mit.edu> <4753@lectroid.sw.stratus.com> <34936@athertn.Atherton.COM> <27fa3350.6bc2@petunia.CalPoly.EDU> Sender: news@cs.psu.edu (Usenet) Organization: Penn State Computer Science Lines: 48 In-Reply-To: araftis@polyslo.CalPoly.EDU's message of 3 Apr 91 19:56:00 GMT Nntp-Posting-Host: sunws5.sys.cs.psu.edu In article <27fa3350.6bc2@petunia.CalPoly.EDU> araftis@polyslo.CalPoly.EDU (Alex Raftis) writes: What makes you say this. Sure RISC is nice, and it has it's place, but look at what advantages RISC gives. It has few intructions, so they execute quickly. That's nice, but each instruction does very little, so you need five instructions to do the same thigns a CISC processor can do. A RISC processor has a lot a registers to work with for speed. Well, the 68040 has sixteen registers, which I find more than plenty when programming. Look at the SPECmarks for the chips. RISC chips are outperforming CISC chips. What are some of its disadvantages? Well, floating point work generally is more difficult. They're also nearly impossible to work with at the assembly level due to the amount of work the programmer has to do to make the advantages of RISC, like pipelining work. cc -O is all you need to know. On the other hand, look at the 68040. It executes instructions at around 1.3 cycles per instuction. It gives you lots of registers. It's easy to work with at the assembly level while its easy to write compilers for. It has a large established base of programmers. It's only major problem is in clock speed. A 25 Mhz 68040 can beat a SPARC at 25Mhz, but the SPAC's top speed is 40Mhz, which will easily beat the 040. Motorola claims to be working on a 50Mhz version of the 040, but I don't have any idea of when they claim this will be released. SPARC isn't a very good RISC. Look at what MIPS is doing. They make the best CPUs. And that 1.3 cycles/instruction is optimal. Do you think that's what we're getting on the NeXT? From NeXT's perspective, they decided to go with the Motorola line. If they should decide to change at this point consider what they would have to do. They would need to 1. rewrite their system software. 2. Many companies would be forced to make major changes to current software packages. 3. They would have to completely rework all that they've done with their hardware. Basically, they'd need to pump a lot of money into doing something that only has dubious advantages. With their current strategy they can work their way into the workstation market with their 25 Mhz cube, which requires low cost memory and support hardware, while they wait for faster versions of the processor to come onto the market. Once this occurs, they can begin to release faster version of the Cube, while still selling their current models as the Workstation for the rest of us. All most companies would have to do is type 'make' to recompile their programs if NeXT switched to a RISC chip. -Mike