Path: utzoo!utgpu!cunews!bnrgate!brtph3!brchh104!brchs1!bnr.ca!rice.edu!sun-spots-request
From: vitec!eric@uunet.uu.net (Eric Parker)
Newsgroups: comp.sys.sun
Subject: Re: How many cycles to load and store on a SPARCstation?
Keywords: Source
Message-ID: <2194@brchh104.bnr.ca>
Date: 26 Mar 91 16:00:00 GMT
Sender: news@brchh104.bnr.ca
Organization: Sun-Spots
Lines: 22
Approved: Sun-Spots@rice.edu
X-Original-Date: Mon, 25 Mar 91 17:39:25 CST
X-Refs:  Original: v10n57
X-Sun-Spots-Digest: Volume 10, Issue 68, message 4
X-Note: Submissions: sun-spots@rice.edu, Admin: sun-spots-request@rice.edu

Here is a program that I wrote to benchmark loads and stores on various
machines.  By inspecting the assembler output (cc -S option) I was able to
determine that the Sun Sparcstation machines using the LSI chipset take 2
cycles for a cache hit read and 6 for a cache hit write.  The read has no
load delay slot (i.e. the processor is stalled while the cache system does
the read).  The write has one delay slot (so back to back writes take 6
clocks).

Hope this helps.

- Eric Paker
(214) 985-2217

[[Ed's Note: Placed in archives on titan. -bdg]]

FTP:	Hostname : titan.rice.edu (128.42.1.30)
	Directory: sun-source
	Filename : ldstr.c
	Filesize : 7064 bytes

Archive Server Address: archive-server@rice.edu
Archive Server Command: send sun-source ldstr.c