Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!cs.utexas.edu!milano.sw.mcc.com!bigtex!james
From: james@bigtex.cactus.org (James Van Artsdalen)
Newsgroups: comp.unix.sysv386
Subject: Re: ESIX and Caching Motherboards
Message-ID: <57583@bigtex.cactus.org>
Date: 3 Apr 91 04:19:15 GMT
References: <824@oss670.UUCP> <1991Mar29.031716.25197@druid.uucp> <1855@svin02.info.win.tue.nl>
Reply-To: james@bigtex.cactus.org (James Van Artsdalen)
Organization: Institute of Applied Cosmology, Austin TX
Lines: 17

In <1855@svin02.info.win.tue.nl>, debra@info.win.tue.nl wrote:

> I believe most 386 machines follow the convention that addresses with the
> most significant bit on are equivalent to the same addresses with that bit
> turned off except for bypassing the cache.

Not exactly, but close.  If the MSB is set, the cycle is not cached
and goes out to the bus - and is not decoded as a local RAM access.
That means that if you have motherboard RAM at address N, a cycle with
address N gets that RAM location, but if the MSB is set, then you get
the AT bus.

There is at least one peripheral card that depends on this scheme to
allow it to be addressed "underneath" motherboard RAM.
-- 
James R. Van Artsdalen          james@bigtex.cactus.org   "Live Free or Die"
Dell Computer Co    9505 Arboretum Blvd Austin TX 78759         512-338-8789