Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!cs.utexas.edu!uunet!littlei!intelhf!ichips!ichips!glew From: glew@pdx007.intel.com (Andy Glew) Newsgroups: comp.arch Subject: Re: Snakebytes (long -- and poisonous?). Message-ID: Date: 3 Apr 91 13:14:52 GMT References: <1998@kuling.UUCP> <8840022@hpfcso.FC.HP.COM> Sender: news@omews63.intel.com (News Account) Organization: Intel Corp., Hillsboro, Oregon Lines: 77 In-Reply-To: cag@hpfcso.FC.HP.COM's message of 2 Apr 91 01:14:30 GMT >Stores take three cycles on the data cache, but if they are followed by >non-data cache accesses, there will be no penalty. Therefore the store >penalty can be zero, one or two states, and the compilers can schedule >accordingly. What are the penalties for back-to-back loads? With/without dependencies? Back-to-back stores? With/without deperndencies? I.e. what are the penalties for the following code fragments: (1) Load followed by independent non-memory code (assuming all registers immediately ready): load r1 := M[imm] add r2 := r3 + r4 add r2 := r3 + r4 add r2 := r3 + r4 (2) Load followed by dependent non-memory code (assuming all registers immediately ready): load r1 := M[imm] add r2 := r3 + r1 add r2 := r3 + r1 add r2 := r3 + r1 (3) Load followed by independent load: load r1 := M[imm] load r2 := M[imm2] (4) Load followed by dependent load: load r1 := M[imm] load r2 := M[r1] (5) Store followed by independent non-memory code: store M[imm] := r1 add r2 := r3 + r4 add r2 := r3 + r4 add r2 := r3 + r4 (6) Store followed by store store M[imm] := r1 store M[imm2] := r2 (7) Store followed by independent load: store M[imm] := r1 load r2 := M[imm2] (8) Store followed by dependent load: store M[imm] := r1 load r2 := M[imm] (9) Load followed by independent store: load r1 := M[imm] store M[imm2] := r2 (10) Load followed by dependent store: load r1 := M[imm] store M[r1] := r2 Have I missed any cases? -- Andy Glew, glew@ichips.intel.com Intel Corp., M/S JF1-19, 5200 NE Elam Young Parkway, Hillsboro, Oregon 97124-6497 This is a private posting; it does not indicate opinions or positions of Intel Corp.