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From: mohta@necom830.cc.titech.ac.jp (Masataka Ohta)
Newsgroups: comp.arch
Subject: Re: Segmented Architectures ( formerly Re: 48-bit computers)
Message-ID: <43@titccy.cc.titech.ac.jp>
Date: 4 Apr 91 04:21:51 GMT
References: <efeustel.669650766@tiger1> <1360009@aspen.IAG.HP.COM>
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Organization: Tokyo Institute of Technology
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In article <1360009@aspen.IAG.HP.COM>
	huck@aspen.IAG.HP.COM (Jerry Huck) writes:

>PA-RISC uses segmentation to extend the addressability of the
>normal general register file.  It is not a partition of these
>registers into pieces.  Segments are 2^32 in size and give
>capability in several areas.

But, by sr(segment register) 4-7, we can address only 1GB of the segment.

So, when we want >4GB, we do general data access with <1GB segment or
with sr1-3 only (sr0 is unusable).

					Masataka Ohta