Path: utzoo!utgpu!cunews!bnrgate!bwdls58!mlord
From: mlord@bwdls58.bnr.ca (Mark Lord)
Newsgroups: comp.arch
Subject: Re: More Snake bytes.
Message-ID: <6371@bwdls58.bnr.ca>
Date: 4 Apr 91 13:24:37 GMT
References: <2004@kuling.UUCP> <8840021@hpfcso.FC.HP.COM>
Sender: mlord@bwdls58.bnr.ca
Reply-To: mlord@bwdls58.bnr.ca (Mark Lord)
Organization: Bell-Northern Research, Ottawa, Canada
Lines: 25

In article <....HP.COM> maf@hpfcso.FC.HP.COM (Mark Forsyth) writes:
<>From: mash@mips.com (John Mashey)
<>
<>the integer performance remains closely on
<>the line of well-implemented single-issue, 1-level cache RISCs,
<>i.e., SPECint = .75-.80X MHz.
<
<The integer "performance" is 2.7 times the 25 MHz R3000 (DEC 5000/200). 
<Speed is an extremely important high performance design technique. If 
<you normalize it out you end up with a truely meaningless indicator of
<performance and one that users shouldn't and don't care about.

From a  comp.arch  point of view, I think the .75-.80X MHz number is of
more value than archecturally irrelevant "my clock is double what yours is"
flame-fests.

So, can we now get back to discussing how best to advance the state-of-the-art
in computer archictectures... ?
-- 
MLORD@BNR.CA  Ottawa, Ontario *** Personal views only ***
begin 644 NOTSHARE.COM ; Free MS-DOS utility - use instead of SHARE.EXE
MZQ.0@/P/=`J`_!9T!2[_+H``L/_/+HX&+`"T2<TAO@,!OX0`N1(`C,B.P/.DS
<^K@A-<TAB1Z``(P&@@"ZA`"X(27-(?NZE@#-)P#-5
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end