Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!rpi!crdgw1!crdos1!davidsen From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) Newsgroups: comp.arch Subject: Re: Segmented Architectures ( formerly Re: 48-bit computers) Message-ID: <3316@crdos1.crd.ge.COM> Date: 5 Apr 91 16:27:50 GMT References: <4919@lib.tmc.edu> <5277@ns-mx.uiowa.edu> Reply-To: davidsen@crdos1.crd.ge.com (bill davidsen) Organization: GE Corp R&D Center, Schenectady NY Lines: 28 In article <5277@ns-mx.uiowa.edu> jones@pyrite.cs.uiowa.edu (Douglas W. Jones,201H MLH,3193350740,3193382879) writes: | People forget history so quickly these days! The Burroughs 5000 and | descendants all used segmented architectures, and they routinely handled | two dimensional arrays as an array of pointers to segments. That is | precisely how Burroughs FORTRAN would have handled the above case, and | if 50000 double's was too big for one segment, it would have automatically | made the array into a 3 or 4 dimensional array, completely hiding the | problem from the programmer without any need for the programmer to specify | some kind of "large memory model" or other such hocum that people are | forced to do on the 8086 family. This is a limitation of the compilers used on the Intel 286 chips, rather than a characteristic of the ships themselves. The compiler vendors could have provided a model (which the user would see only on the compiler command line) with 32 bit ints, and the exact hiding of detail you mention. I suggested this to several vendors while beta testing their compilers. It's a little harder to fault the 386 chips, since their limitations are the same as other 32 bit machines and segmentation is not visible. There is the ability to handle more than 4GB by using the segments, but I don't see either the capability or the commercially viable demand right now. -- bill davidsen (davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen) "Most of the VAX instructions are in microcode, but halt and no-op are in hardware for efficiency"