Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!usc!apple!agate!eris.berkeley.edu!doug From: doug@eris.berkeley.edu (Doug Merritt) Newsgroups: comp.arch Subject: Re: Low End NeXTs (was Re: Desktop publishing) Message-ID: <1991Apr5.172533.6717@agate.berkeley.edu> Date: 5 Apr 91 17:25:33 GMT References: <27fa3350.6bc2@petunia.CalPoly.EDU> <1991Apr03.232400.1560@kithrup.COM> <1991Apr4.125122.1@capd.jhuapl.edu> Sender: usenet@agate.berkeley.edu (USENET Administrator) Organization: University of California, Berkeley Lines: 31 In article <1991Apr4.125122.1@capd.jhuapl.edu> waltrip@capd.jhuapl.edu writes: > He observes that "Few compilers use any of the nifty instructions that > a CISC has." I believe I read recently that RISC was based on the > observation that, in fact, only about 30% of the instructions in CISC > computers were used by compilers. The rest of the instructions, for > all practical purposes, were just excess baggage. Not only that, but even when the other instructions and addressing modes *are* used, it doesn't help that much. A few years ago I wrote a compiler (code generator, actually) that used essentially all of the addressing modes, and almost all of the instructions in the 68020. The results were not encouraging. In the absolute best case, static code density improved maybe 25%, but usually closer to 0% (break-even). This is because the extra features almost always take as many bytes to encode in a single fancy instruction as the equivalent multi-instruction sequence. Dynamic code speed showed similar results. (The effort wasn't wasted, though, because the original prototype code generator was highly suboptimal even for simple instructions.) Anyway, the point is that even if compilers *do* use every possible feature of a CISC, it still usually won't make the CISC s/w competitive with RISC s/w. CISC cpus almost never put sufficient h/w optimization into the support of the fancy instructions. (There are exceptions to this, of course, and I haven't been watching the 030 and 040 to see how they do in this regard. CISC may yet rise again, but not until after superscalar RISC has been completely exploited.) Doug -- Doug Merritt doug@eris.berkeley.edu (ucbvax!eris!doug) or uunet.uu.net!crossck!dougm