Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!elroy.jpl.nasa.gov!decwrl!mcnc!uvaarpa!murdoch!madras!clc5q
From: clc5q@madras.cs.Virginia.EDU (Clark L. Coleman)
Newsgroups: comp.arch
Subject: Re: Snakebytes (long -- and poisonous?)
Message-ID: <1991Apr5.183233.26573@murdoch.acc.Virginia.EDU>
Date: 5 Apr 91 18:32:33 GMT
References: <1996@kuling.UUCP> <32580012@hpcuhe.cup.hp.com>
Sender: usenet@murdoch.acc.Virginia.EDU
Organization: University of Virginia Computer Science Department
Lines: 20

In article <32580012@hpcuhe.cup.hp.com> linley@hpcuhe.cup.hp.com (Linley Gwennap) writes:
>I'd like to take a moment to respond to comments that the Series 700
>has achieved its high performance due primarily to high (66 MHz) clock
>frequencies resulting from advanced CMOS processes.  While HP's IC
>processes are as good as anyone's, the Series 700 CPU is implemented
>in a 1.0 micron, 3-metal-layer CMOS process which is pretty standard
>throughout the industry.  It is nearly identical to IBM's 1.0 micron
>process used in their 20-30 MHz RS/6000s, and not as dense as the
>0.8 micron process used in IBM's 41 MHz Model 550.

Maybe you could clarify this for me. I read that the main CPU was 1.0 micron
geometry and the Texas Instruments floating point coprocessor was 0.8 micron
from a TI process. It sounds like the floating point unit has a process
at least as good as any competitors' processes, and the main CPU and cache
chips are about average for this market segment. Is this right?

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"The use of COBOL cripples the mind; its teaching should, therefore, be 
regarded as a criminal offence." E.W.Dijkstra, 18th June 1975.
|||  clc5q@virginia.edu (Clark L. Coleman)