Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!daver!cypress!murf From: murf@cypress.UUCP (Colin Murphy) Newsgroups: comp.arch Subject: Re: More Snake bytes. Summary: consider also process and packaging Message-ID: <815@cypress.UUCP> Date: 9 Apr 91 19:17:37 GMT References: <2004@kuling.UUCP> <8840021@hpfcso.FC.HP.COM> <569@diab.se> <1991Apr5.191331.27524@murdoch.acc.Virginia.EDU> Lines: 104 The tradeoffs made in processor micro-architecture are influenced by process capability and package availibility. The process capability consists not only of a delay per gate number, but also a number for the total count of transistors and wires possible per die. I am very familiar with the ROSS Technology SPARC 40Mhz 7C601 CPU, and barely familiar with the MIPs architecture and chips. First some data on process: ( Cypress Semiconductor is our foundry for this ) ROSS Tech. H-P MIPs Gate oxide 195 Ang 200 Ang exact unknown, IDT and Performance do have comparable processes available. In terms of transistor physics the first two processes are comparable. (I no longer even talk about Leff because with the advent of LDD and dished punch through control implants Leff is a function more of the particular measurement technique used than of reality.) So, at first glance H-P has just out engineered the rest of us. Now lets check out the "secondary" process characteristics. ROSS Tech. H-P MIPs contacted metal 1 pitch 4.0u 2.6u ?about the same as cypress? contacted metal 2 pitch 4.6u 2.6u ?a little larger than cypress? contacted metal 3 pitch none 6.0u none die size (per side) 310 mils 550 mils ?~330 mils, differs by vendor 7.9mm 14.0mm ?~8.4mm transistors 104K 479K ?<<200K, if memory serves I do not consider the H-P process to use the same generation of interconnect, it is at least one generation more advanced for pitch, yield, and the use of three levels of metal interconnect. That is, H-P puts a lot more wires and transistors, closer together, on the snake, than are on either the 7C601 or the R3000A. clc5q@virginia.edu (Clark L. Coleman) writes: >In article <569@diab.se> pf@diab.UUCP (Per Fogelstr|m) writes: >>If we could push the clock frequency for the R3000 up to 66Mhz it would, >>if we scale the results, perform equally well with the HP9000/730. > >And will the HP9000/730 sit still while you do that? Can the R3000 be >implemented TODAY in HP's technology at 66MHz ? Does anybody really >believe that? Why not? I do, with some corrections to long paths, and while I am another axe grinder, I am grinding mine to use on MIPSco, and H-P and IBM. The R3000A is limited by using an obsolete package so that it will be pin compatible with the previous designs, as would any cpu that used the same pin out for more than three years. Let's look at package technology, ROSS Tech. H-P MIPs 7C601 snake R3000 number of pins 207 408 176 The number of pins used on the 7C601 was limited by both the package technology available and the size of the die coupled with the minimum pad pitch on the die. What was the effect of this? H-P has a full harvard chip, with a 64 bit wide data bus, the 7C601 uses a 32 bit wide combined instruction and data bus with one address bus, the R3000 uses separate 32 bit instruction and data buses with a multiplexed address bus. The H-P chip has a built in advantage, one that is especially important for double precision floating point. BTW, the multiplexed address bus is probably what is limiting the R3000A to 33 MHz systems, I would guess that the chip itself is more capable, not that the end user cares. Historical note: The intel ?3001? 2 bit bit-slice and the 8008 were made obsolete by the AMD 2901 4 bit bit-slice and the intel 8080. Why? Because the first two were in 18 pin packages, and the second two were in the brand new 40 pin package, circa 1974-76. -- quote out of order -- >Seriously, I cannot believe I am reading so many people claim that MHz >is 100% implementation, 0% architecture. >I said to myself years ago that if HP were to implement the HP-PA stuff in >state of the art semiconductors, they would blow away the competition. >Prophecy fulfilled in 1991; the competitors ARE using a process that is just >as good as HP's, other postings notwithstanding; and the detractions I see on >this thread bespeak a lack of architecture understanding, or commercial envy >and axe-grinding in a few cases. What is there about the HP-PA architecure that allows for a faster implementation given equal levels of technology? I would like to know so I can go beat up on some architects. 8^) Seriously, the next SPARC chips will have more transistors and wires per die and use more pins. This is the result of designing in 1989-91 as opposed to 1986-88, and has nothing to do with ISA, but everything to do with micro architecture and economics. -- Colin Murphy - ROSS Technology, Inc, daver!cypress!murf - (408) 943-2887" "The many, the humble, the implementors of the SPARC custom CMOS IU"