Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!pacific.mps.ohio-state.edu!linac!att!ucbvax!pasteur!cory.Berkeley.EDU!navas From: navas@cory.Berkeley.EDU (David C. Navas) Newsgroups: comp.sys.amiga.graphics Subject: Re: NEC 3D owners please read! Message-ID: <12592@pasteur.Berkeley.EDU> Date: 8 Apr 91 21:11:18 GMT References: <236@nos850.UUCP> <18d469bd.ARN0f0e@cbmami.UUCP> <1991Mar20.164339.8640@news.iastate.edu> <16042.27eb7eae@levels.sait.edu.au> <12505@pasteur.Berkeley.EDU> <16145.2800a36e@levels.sait.edu.au> Sender: news@pasteur.Berkeley.EDU Reply-To: navas@cory.Berkeley.EDU Lines: 49 In article <16145.2800a36e@levels.sait.edu.au> etac@levels.sait.edu.au writes: >When I said "switch to PAL mode instead of Multisync mode" I mean manually >changing the Enhancer-deinterlacer switch on the back of the A3000. Nah, don't do that... The Enhancer is automatically turned off while in MultiSync modes. You'll want to leave it on in PAL -- should look a lot better, less flickery that way. Or am I misunderstanding you? >The Overscan Editor tool can do it from software somehow. According to it, >PAL is Enhancer-off and Muktisync is Enhancer-on. Or at least that's >the way it comes up on my machine What software were you using to get this info? I don't see this in my release -- but I have the advantage of being a developer and getting upgrades to WB releases :) Anyway -- for multisync, you don't need to disable the Enhancer, because it disables itself. For PAL you want the Enhancer *ON* to eliminate flicker in interlace modes. In multisync I can't seem to move the screen to the far right -- but then the multisync uses the right portion of the screen to increase it's vertical resolution to x480, instead of x400 [for 60Hz]. That's my best guess at the moment. -Dave > >> >>> Has anyone else noticed this, or know why the multisync picture is so >>>different from the PAL picture.( why is it smaller? why isn't it centred?) >> >> Yes I have noticed it. >> No I don't know why :( Probably something to do with the fact that >> Productivity pushes those chips way out on the performance curve :) >> >>>Andrew Chalmers >> >> David Navas navas@cory.berkeley.edu >> 2.0 :: "You can't have your cake and eat it too." >> Also try c186br@holden, c260-ay@ara and c184-ap@torus > >Andrew Chalmers. etac@lv.sait.edu.au David Navas navas@cory.berkeley.edu 2.0 :: "You can't have your cake and eat it too." Also try c186br@holden, c260-ay@ara and c184-ap@torus