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From: jmasters@fxrs.intel.com (Justin Masters)
Newsgroups: comp.sys.amiga.hardware,comp.sys.amiga.tech
Subject: Re: 68000 timing
Message-ID: <355@fxrs.intel.com>
Date: 5 Apr 91 21:32:35 GMT
Article-I.D.: fxrs.355
References: <3319@hexagon.se>
Reply-To: jmasters@fxrs.intel.com (Justin Masters)
Organization: Intel FMD, Folsom, CA
Lines: 47

In article <3319@hexagon.se> frix@hexagon.se (Fredrik Rothamel) writes:
|I've got this small question...
|
|Does anyone have som info on 68000 signal timing ?

I have the book on the spec-book for the  68000 in front of me.  Shhhhh...
don't tell my boss.  

Actually, I'm taking a course, so I have to have it.

|
|I'm currently interested in how long the processor can wait for a DTACK
|signal, but info on other signals would also be great. 

It's DTACK# (active low)

Well, let's just say that for an asynchronous operation (which DTACK# is used
for) the processor can wait a loooong time, unless something terminates the
bus cycle.  DTACK# is a "Data Transfer ACKnowledge" signal. 

If used in a read cycle, DTACK# is asserted, the data is latched on the data
bus and the bus cycle ends.  If in a write cycle, when DTACK# is asserted, it
assumes that the data was accepted by whatever peripheral requested the data,
and ends the bus cycle.  If DTACK# is not seen in S4 (S0-S7 consitutes a bus
cycle), then wait states are generated, and the bus cycle doesn't end, unless
ended by some other bus termination method (reset, bus error, address errors,
trace, interrupts, illegal instructions, privilege violations, TRAP, TRAPV,
CHK and zero divide exceptions).

Hope that helps. :-)

The data manual is really cheap.  I bought mine from a college bookstore for
$1.35.

|
|Thanx in advance.
|-- 
|	-- The above expressed opinions are completely my own. --
|Fredrik Rothamel					    Fidonet 2:204/117.3
|frix@hexagon.se				   ...!sunic!kullmar!pkmab!hexagon!frix


-- 
"He also emphasized that the glossy advertising circulars, etc., are instant
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---------------------------------------------------------------------------
   Justin Masters                       jmasters@fws136.intel.com