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From: rhyde@ucrmath.ucr.edu (randy hyde)
Newsgroups: comp.sys.apple2
Subject: Re: HLLs vs. Assembly
Message-ID: <13347@ucrmath.ucr.edu>
Date: 5 Apr 91 08:09:12 GMT
References: <15682@smoke.brl.mil> <13275@ucrmath.ucr.edu> <1991Apr4.185435.28753@midway.uchicago.edu>
Organization: University of California, Riverside
Lines: 33

>>>>
One fact that hasn't yet been addressed in this discussion is the existence
of new processor architectures (RISC especially) of such complexity that you
REALLY DO NEED A COMPILER TO WRITE EFFICIENT SOFTWARE.  I'm talking about
things like multi-stage instruction pipelines which must be kept full to
achieve good performance.  What about branch prediction and
register/pipeline interlock, which might involve actually changing the
apparent order of instructions?  Do you really want to have to keep track
of stuff like that, when bunches of very smart people have already written
compilers that will do it for you?  Machine language isn't always the answer,
and I suspect that will become more true in the future.
<<<<

I let some people sucker me into believing this.  I swear I'm gonna teach
myself SPARC assembly before I make any cracks one way or another on this
topic.  However, please allow me to make one quick comment:  Why on earth
can't we write an *optimizing assembler* which rearranges instructions
to keep the queues full, and warns you if you're not using the registers
as efficiently as you possibly could?  This would address the statement
that one really needs a compiler to write efficient code on a RISC.

Remember, it isn't just the instruction mix which makes human-written
assembly language programs better than machine-written assembly language
programs, it's the intelligence of the auther and the way s/he thinks
about the solution to the problem.  

As an aside (which I'm sure will start another flaming thread), I suspect that
RISC's days are numbered.  Most of the advantages of RISC are being implement-
ed into CISC, and what CICS will never be able to handle, LIWCs will blow
both RISC and CISC away on.  I suspect that VCISC computers, once someone
comes up with a better system bus structure (e.g., optical) will prove
that RISC is a dead end.
*** Randy Hyde