Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!think.com!snorkelwacker.mit.edu!bloom-beacon!eru!hagbard!sunic!mcsun!ukc!mucs!els!camm From: camm@els.ee.man.ac.uk (Ian Camm) Newsgroups: comp.sys.atari.st Subject: STe SIMM Pin Layout Message-ID: <2371@m1.cs.man.ac.uk> Date: 5 Apr 91 13:36:16 GMT Sender: news@cs.man.ac.uk Organization: Manchester Computer Centre, University of Manchester UK Lines: 19 Hi All, I have just upgraded my 520STe to 2 Megs so I now have 2 1/4M SIMM's rattling about in a draw. A colleague of mine is working on a project at home and could use this RAM. So what I want to know is, what is the pin layout for these SIMM's. If you have the information or can point me in the right direction I would be most grateful. Thanks in advance, Ian -- Ian Camm | JANET: camm@uk.ac.man.ee.els Dept. of Electrical Engineering | ARPA: camm@els.ee.man.ac.uk University of Manchester, England | UUCP: ...!!ukc!man.ee.els!camm Disclaimer: If you think I need one make it up yourself.