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From: huck@aspen.IAG.HP.COM (Jerry Huck)
Newsgroups: comp.sys.hp
Subject: Re: HP9000-7XX overflow : Technical question
Message-ID: <2130010@aspen.IAG.HP.COM>
Date: 5 Apr 91 18:08:13 GMT
References: <9934@discus.technion.ac.il>
Organization: HP Information Architecture Group - Cupertino, CA
Lines: 54

>In comp.sys.hp, devil@techunix.BITNET (Gil Tene) writes:
>    Hello HPeople,
>    Question boils down to (explanation of motivation below) :
>    How do I do integer overflow detection on a 9000-7xx ?
>            (using machine code is OK)
>    Is it possible? Is it "cheap"? can it be done? can it be done without
>    using a whole signal call mechanism every time an overflow occurs?

The 9000-7xx and the 9000-8xx are both implementations of the PA-RISC
architecture.  The most effective way to do in-line overflow tests is
to use instruction nullification.  The special case of addition can be
done in a single instruction.

All compuations instructions (add, sub, add with carry,...) allow
conditional nullification (cancelling) of the next instruction.  For
your purposes the sequence might be:
    ...
    sub,NSV  r1,r2,r3                    ;do an operation and skip the next
                                        ;if no signed overflow.
    depi     1,OVBIT,1,simulatedPSW     ;set some bit (depi=deposit immediate)
    ...                                 ;in some magic location on overflow.

This turns those instructions that are simulating overflow setting
instructions into a 2 instruction sequence.

An alternative exists for 32 bit addition.  If overflow is unlikely,
you could use the instruction:

    ...
    addb,SV  r1,r2,setoverflow         ;r2<-r1+r2. Branch only on overflow.
    <delay slot>                       ;next instruction.  Will be executed
                                       ;if branch is taken.  You could also
                                       ;cancel this if necessary.
rejoin:
    ...


setoverflow:
    b        rejoin
    depi     1,OVBIT,1,simulatedPSW     ;set some bit (depi=deposit immediate)
    ...                                 ;in some magic location.


This style requires that 2 instruction out-of-line fix-up for
each occurrence of an ADDB,SV occurrence.

In your 68K hosted emulation, what is the overhead per simulated
instruction that needs to record overflow?  Do you put those flag
tests (I assume a branch on condition) after each simulated potentially
overflowing instruction or can you collect a bunch of operations before
testing for overflow?

Hope this helps,
Jerry