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From: jfriedl@NATASHA.MACH.CS.CMU.EDU (Jeffrey Friedl)
Newsgroups: comp.sys.m88k
Subject: Re: Exception handling in the 88's
Message-ID: <1991Apr9.014849.145@cs.cmu.edu>
Date: 9 Apr 91 01:48:49 GMT
References: <28961@dime.cs.umass.edu>
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Reply-To: jfriedl@NATASHA.MACH.CS.CMU.EDU (Jeffrey Friedl)
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In article <28961@dime.cs.umass.edu>, black@par1.cs.umass.edu (David K. Black) writes:

|> there apears a discussion of two methods for exception processing
|> in the 88's.  To summarize:
|> 
|> Method 1: Disable interrupts etc and don't save any context to memory.
|> Use the rte instruction to restore control registers.  Shadowing remains
|> disabled and a non-trap exception will crash the machine.
|> 
|> Method 2: The exception handler saves control register context to memory
|> and shadowing is re-enabled, allowing for nested exceptions.  
|> 
|> My question is: Under what cicumstances is the first method acceptable?

Well, any time that you don't need to do anything because of the
interrupt, or if what you need to do is reeeeeeally small.

|> Are there any OS code writers within "the sound of my voice" who have 
|> actually confronted this problem?

I wrote the exception handler for the Omron Luna/88k (4-processor machine,
runs mach).  I had none of the 'method 1' cases.

|> In general, would anyone  care to comment on exception processing in 
|> the 88's in general?  Any caveats to be known? etc.

Keep abreast of the 'General Information' and 'Errata' sheets for the
processor.  My understanding of the 'General Information' items is that
they are bugs that won't be fixed.  For example (and from the top of
my head -- it's been awhile -- best if you check with Motorola), the
first of the two instructions per vector slot must be a NOP.  This is
pretty important to know! There are various others....

I'd love to get my hands on other 88k machines, to test some wild cases.
For example, consider the following executed in user space:

        load r2/r3 with a HUGE number, load r4/r5 with NaN.
	fmul.ddd r31, r2, r2
	fadd.ddd r6, r4, r4

If you've written an exception handler, you should know why this
is an interesting situation.  If you haven't written a handler,
but will soon, you should think about stuff like this! (-:

	*jeff*
------------------------------------------------------------------------------
Jeffrey Eric Francis Friedl        jfriedl@cs.cmu.edu -or- jfriedl@omron.co.jp
Omron Corporation, Section RZE, Shimokaiinji, Nagaokakyo-city Kyoto 617, Japan
Currently, visiting researcher to the MACH project, Carnegie Mellon University