Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!cs.utexas.edu!uunet!infonode!ingr!b11!dclark
From: dclark@b11.ingr.com (Dave Clark)
Newsgroups: comp.arch
Subject: Re: Instruction Scheduling
Keywords: SPEC compilers CDC Mips
Message-ID: <1991Apr10.131341.26357@b11.ingr.com>
Date: 10 Apr 91 13:13:41 GMT
References: <32097@shamash.cdc.com> <1991Apr8.224717.14402@aero.org>
Organization: Intergraph Corp. Huntsville, AL
Lines: 38

jordan@aero.org (Larry M. Jordan) writes:

>Where and when does instruction scheduling/reorganizing occur?  Is
>this function performed by the HOL compilers?  (If so, the symbolic
>assembly I'm reading obscures this fact.  If not, then during
>assembly?)  

Yes and no.  Most HOL compilers do some sort of optimizing on the
back-end.  Although I haven't (yet) seen an assembler that does
optimizations, I have seen utilities that can optimize assembly
code (part of an HOL compiler back-end).

One of the compilers I'm using actually does instruction reordering
within the linker!

>In a word or two, could someone summarize the pros/cons for either
>approach (HOL or independent lang. independent pass)?

HOL or high-level intermediate representation: Control structures are
more easily recognizable.  Restructuring is straightforward.  Machine-
specific optimizations are often omitted from this phase so that the
bulk of the compiler can be easily ported.

Assembly level: This is a good place to put machine-specific optimi-
zations.  Instruction timing and reordering is a simple search prob-
lem, especially on the advanced RISC chips.

>--Larry 


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   Dave Clark                     |
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