Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!spool.mu.edu!cs.umn.edu!matterhorn!dahl
From: dahl@matterhorn.ee.umn.edu (Peter Dahl)
Newsgroups: comp.arch
Subject: Re: Instruction Scheduling
Keywords: SPEC compilers CDC Mips
Message-ID: <1991Apr11.145222.11441@cs.umn.edu>
Date: 11 Apr 91 14:52:22 GMT
Article-I.D.: cs.1991Apr11.145222.11441
References: <32097@shamash.cdc.com> <1991Apr8.224717.14402@aero.org> <1991Apr10.131341.26357@b11.ingr.com>
Sender: news@cs.umn.edu (News administrator)
Organization: University of Minnesota, Minneapolis, EE dept.
Lines: 27
Nntp-Posting-Host: matterhorn.ee.umn.edu

In article <1991Apr10.131341.26357@b11.ingr.com> dclark@b11.ingr.com (Dave Clark) writes:
>jordan@aero.org (Larry M. Jordan) writes:
>
>>Where and when does instruction scheduling/reorganizing occur?  Is
>>this function performed by the HOL compilers?  (If so, the symbolic
>>assembly I'm reading obscures this fact.  If not, then during
>>assembly?)  
>
>One of the compilers I'm using actually does instruction reordering
>within the linker!
 ^^^^^^^^^^^^^^^^^
Register allocation can be also done by the linker. See "Register 
Windows vs. Register Allocation", David Wall, Proceedings of the
SIGPLAN '88 Conference on Programming Language Design and Implement-
ation, Atlanta, GA, June 22-24, 1988.

This paper describes why the author thinks that link time code 
modification is effective. He uses profiling of usage frequencies
to make decisions. However he only claims results as good as
compiler based schemes and nearly as good as register windows. The
part that is nice about this scheme is that it could set you up for
other global optimizations, depending on the types of information
the compiler tucks away for you to work with.
--

peter dahl@src.honeywell.com
I had fun once, and it wasn't anything like this