Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!caen!uflorida!travis!paulb From: paulb@ssd.csd.harris.com (Paul Beusterien) Newsgroups: comp.arch Subject: Re: Instruction Scheduling Message-ID: Date: 11 Apr 91 17:00:41 GMT References: <32097@shamash.cdc.com> <1991Apr8.224717.14402@aero.org> <1991Apr10.131341.26357@b11.ingr.com> Sender: news@travis.csd.harris.com Organization: Harris Computer Systems Division Lines: 35 In-reply-to: meissner@osf.org's message of 11 Apr 91 15:41:14 GMT In article meissner@osf.org (Michael Meissner) writes : } } However at the assembly level can be too late if the latency is high } enough. For example, if the compiler reuses register temps quick } enough, the assembler doesn't have a chance to do aggresive code } movement, since the next instruction reuses the register that you are } waiting to be reloaded. For example, if the code sequence is: } } a = b; } c = d; } } a compiler on a load/store machine might rewrite this as: } } reg = b; } a = reg; } reg = d; } c = reg; } } wheras if you have a latency, and you have plenty of registers, you } really want to rewrite it as: } } reg1 = b; } reg2 = d; } a = reg1; } c = reg2; This example shows the value of a register reallocator that happens as a pre-pass to instruction scheduling. Doing the analysis to detect the above case is much simpler than generic register allocation and it can be done with basically an O(n) traversal over the assembly code. -- Paul Beusterien paulb@ssd.csd.harris.com Harris Computer Systems {uunet,mit-eddie,novavax}!hcx1!paulb Ft. Lauderdale, FL voice: (305) 973 5270