From: maf@hpfcso.FC.HP.COM (Mark Forsyth)
Date: Mon, 8 Apr 1991 00:23:12 GMT
Subject: Re: Re: More Snake bytes. (X/MHz)
Message-ID: <8840024@hpfcso.FC.HP.COM>
Organization: Hewlett-Packard, Fort Collins, CO, USA
Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!hp-col!hpldola!hpysllb!hpyhde4!hpcc05!hplabs!hpfcso!maf
Newsgroups: comp.arch
References: <12914@goofy.Apple.COM>
Lines: 39


<To summarize, John Mashey has spoken of SPECint / MHz as a measure of 
<architecture independent of absolute MHz, while Mark Forsyth has indicated 

This is a reasonble measure of architectures if the speed is similar.
It is more difficult to achieve low CPI at higher speeds since memory
speed doesn't always scale with processor speed, producing higher cache
and TLB miss penalties. For comparing 33 to 66MHz designs it probably 
doesn't make a big difference, except in some of the more cache intensive
benchmarks (like some SPEC FP benchmarks).

<that ability to build a higher MHz implementation given the same process 
<technology is also a relevant measure of an architecture, stating that 
<HP's process technology is typical.  Mashey countered that HP's technology 
      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
HP's CMOS technology is excellent and very well suited to high-speed
designs. The other poster who made that statement has been corrected.
The only "typical" thing about it is the 1.0 micron channel lengths.

<is faster than average.
<
<The unanswered question seems to be: can the HP architecture be designed 
<with fewer gate delays than others?  I think there are 33MHz R3000s and 66 
<MHz Snakes.  Is this entire difference attributable to process technology? 
<When superscalar implementations become common, a similar question will 
<arise for them, and it's not obvious to me that the architectures which 
<allow the fewest gate dealys and best CPI numbers in a single-issue design 
<will still have the advantage in a multiple-issue design.

Speed is a function of circuit design methodology, processor partitioning,
chip floorplanning, feature set, etc. etc. as well as technology and 
architecture. All of these are interrelated and you have to review all 
of the choices with every generation to determine the best way to optimize 
cost, performance, and schedule for each specific product. Every RISC 
architecture is capable of higher speeds or superscalar implementations.
It will be interesting to compare all of the choices for the next generation.

- Mark Forsyth (my opinions, not HP's)
  maf@hpesmaf