Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!hplabs!hpcc05!hpcuhb!hpcuhe!linley
From: linley@hpcuhe.cup.hp.com (Linley Gwennap)
Newsgroups: comp.arch
Subject: Re: Re: Snakebytes (HP process technology)
Message-ID: <32580016@hpcuhe.cup.hp.com>
Date: 8 Apr 91 22:16:32 GMT
References: <40812@cup.portal.com>
Organization: Hewlett Packard, Cupertino
Lines: 26

(Michael Z Slater) notes:

> IBM may have 3-layer
> metal, but I am not aware of any commercially available microprocessor 
> fabricated in a 3-layer metal process.  I'm not a process expert by a long
> shot, but from what I understand, there is a speed advantage here.

The third metal layer is indeed an advantage for high speed microprocessors.
It can allow lower skew on internal clock distribution networks, more area
devoted to power/ground busing to reduce noise, and often shorter signal
interconnects which minimize RC delays.  It is not, however, as significant
as shrinking the overall device size below one micron.  While HP's IC
fabrication processes are very good, they are not out on the "bleeding
edge", so there's plenty of room for future improvement.  (For bleeding
edge, try TI's 0.8 micron BiCMOS process!)

To clarify another inquiry, of the three large chips (CPU, FPU, MC) in
the Series 700, two are fabbed by HP.  The FPU is fabbed by TI in a 0.8
micron, two metal-layer CMOS process.  While Hitachi is not involved in
the Series 700, they have licensed the PA-RISC architecture and are
expected to produce PA-RISC chips in the future.

---------------------------------------------------------------------------
DISCLAIMER:  The views expressed here do not		Linley Gwennap
represent the views of the Hewlett-Packard		PA-RISC Marketing
Company.  Caveat emptor.				Hewlett-Packard