Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!hplabs!hpda!hpcuhb!hpcuhe!linley
From: linley@hpcuhe.cup.hp.com (Linley Gwennap)
Newsgroups: comp.arch
Subject: Re: Re: Snakebytes (long -- and poisonous?).
Message-ID: <32580017@hpcuhe.cup.hp.com>
Date: 11 Apr 91 21:33:45 GMT
References: <1998@kuling.UUCP>
Organization: Hewlett Packard, Cupertino
Lines: 20

(Dan Westerberg) asks:
> Please correct me if I'm wrong since I design gate arrays, but are
> 3-metal-layer processes *average*?

Let me clarify.  HP's IC processes are among the industry leaders for
large-scale CPU designs (CPUs tend to push the boundaries).  I would
not call our IC processes "average".  The 3-metal-layer is one area
where we are probably ahead of most of the industry.  In the area of
device size, at 1 micron we are with the industry leaders but not
really pushing the limits.  In short, there are plenty of technological
advances left to apply to the Series 700 CPU chip.

The FPC chip is fabricated by Texas Instruments in a different process.
This chip uses a 0.8 micron, 2-metal-layer TI process.  This denser
process helps keep the cost of the FPC chip down.

---------------------------------------------------------------------------
DISCLAIMER:  The views expressed here do not		Linley Gwennap
represent the views of the Hewlett-Packard		PA-RISC Marketing
Company.  Caveat emptor.				Hewlett-Packard