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From: linley@hpcuhe.cup.hp.com (Linley Gwennap)
Newsgroups: comp.arch
Subject: Re: Info on HYPERSTONE comming here
Message-ID: <32580019@hpcuhe.cup.hp.com>
Date: 11 Apr 91 22:15:16 GMT
References: <7706@uklirb.informatik.uni-kl.de>
Organization: Hewlett Packard, Cupertino
Lines: 15

(Reinhard Kirchner) posts Hyperstone info:

>      hyperstone E1: 25 MIPS maximum speed with standard DRAMs

Thanks for posting this information.  It looks like a nice little
embedded controller.  Any performance specs other than the 25 MIPS
maximum?  I assume this is a 25 MHz processor that can execute one
instruction per cycle as long as the program fits in the 128-byte
instruction cache.  With standard DRAMs, the cache miss penalty must
be severe.  Do you have any price and availabilty numbers?

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