From: bsb@hp-lsd.COS.HP.COM (Brett Baumberger)
Date: Fri, 12 Apr 1991 19:37:11 GMT
Subject: Re: STD Bus
Message-ID: <8190011@hp-lsd.COS.HP.COM>
Organization: HP Logic Systems Division - Col
Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!hp-col!hpldola!hp-lsd!bsb
Newsgroups: comp.os.cpm
References: <".3-Apr-91.12:19:52.EST".*.Michael_D._Sprague.wbst311@Xerox.com>

STD bus was designed around Intel 8085 bus signals.  That gives
you the following signals:
   A0-A15 for 64k of memory;
   D0-D7  8 bit data bus
   IO/M*  select between memory or I/O
   a couple of interrupt lines
   reset
   clock

Notice I show a de-multiplexed Address/Data bus.  De-multiplexing
is performed on the processor card.  This enabled Motorola-based
processors to implement STD as well.  I forgot to mention R/W
in the signals above.

I once designed and implemented a system based around STD for
an unnotable government subcontractor.  It worked, it was
cheap.  It was easy to replace parts if needed.  It was
modular, which is one of STD's design goals.  Just take a
cpu card, add enough memory cards for your app, add I/O.
Complete system.....Just add firmware.

Brett Baumberger