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From: rudolpe@jacobs.CS.ORST.EDU (Eric Hans Rudolph)
Newsgroups: comp.sys.amiga.hardware
Subject: 14Mhz Hack
Message-ID: <1991Apr12.182537.1835@lynx.CS.ORST.EDU>
Date: 12 Apr 91 18:25:37 GMT
Article-I.D.: lynx.1991Apr12.182537.1835
Sender: rudolpe@jacobs.cs.orst.edu
Organization: Oregon State University, CS Dept.
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I have been trying to build the 14Mhz hack in it's various forms for a while 
now. I can't seem to get any of the versions to work, probably from what I 
think is poor thought on the designer's part. Now I think I understand that
the 68k is aysynchronous, and will wait for VPA* or Dtack* or Buss Error...
I know theoretically, it will wait for one of those above forever.
All this business about syncing Dtack* so that the 68k will start a bus
cycle on the correct clock phase is confusing me. I thought Gary monitored
when the 68k entered a bus cycle and corrected it if it was in the wrong phase.

Is there anyone out there who can tell me just how long I can hold off Dtack*
and where I can have it asserted, assuming that the 14Mhz 68k starts the
bus cycle S0 at the same time it WOULD have if it were running at 7Mhz?
(is this a valid assumption? I am XORing CDAC (not inverted) with 7Mhz. )

Is it possible to get this hack to work?

If I divide down the 1.4Mhz Eclock by 2 with a flip flop, the new E clock
will be at a 50/50 duty cycle, assuming I can get VPA* and VMA* to work,
does the 50/50 pose a problem?

Any comments? I am desperate...

rudolpe@jacobs.cs.orst.edu