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From: rudolpe@jacobs.CS.ORST.EDU (Eric Hans Rudolph)
Newsgroups: comp.sys.amiga.hardware
Subject: 14Mhz Hack, revisited...
Message-ID: <1991Apr13.073956.29605@lynx.CS.ORST.EDU>
Date: 13 Apr 91 07:39:56 GMT
Sender: rudolpe@jacobs.cs.orst.edu
Organization: Oregon State University, CS Dept.
Lines: 24
Nntp-Posting-Host: jacobs.cs.orst.edu

Okay, I am here in the lab on the logic analyzer and have found out a couple
of things... First, if you use a 500, and want to get a 14mhz signal from
XORing CDAC* and 7, don't pull it off of the Expansion IO slot. The signal
is WAY funny and when you XOR it with 7, it gives a bad stomach ache.
Pull the CDAC off of agnus. It's better shaped and will provide a clean
14Mhz. The rising edge is kinda humpy, but maybe my chip is slow. It's only
LS. Furthermore, and I haven't found a solution yet, when you double the
clock speed, of course the cycle should be shorter. AS* will go low
and the CPU will wait for DTACK* or VPA*. If you sync up the DTACK* with
the 7MHZ clock, so that supposedly it will end on a correct cycle, on some
memory reads, the REAL DTACK* STILL STAYS ASSERTED. If the cycle was a 
slow 7mhz one, it would have been deasserted at the end of state 6/7, 
however, in the faster mode, it overlaps into the next cycle. My first
impression is that to fix this, one needs to hold of generating AS* to
the device until the old DTACK* deasserts.

Can anybody clarify me on this subject??? This is .hardware...!

The above circuit design I am talking about is the New 14mhz hack, which
doesn't work. I think I am close to providing one that does.

Also, just DON'T use LS chips. They are way too slow.

rudolpe@jacobs.cs.orst.edu