Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!pacific.mps.ohio-state.edu!linac!att!ucbvax!gnh-starport.cts.com!whitewolf From: whitewolf@gnh-starport.cts.com (Tae Song) Newsgroups: comp.sys.apple2 Subject: Re: HLLs vs. Assembly Message-ID: Date: 13 Apr 91 04:39:01 GMT Sender: daemon@ucbvax.BERKELEY.EDU Organization: The Internet Lines: 25 X-Unparsable-Date: Fri Apr 12 91 at 20:33:05 (EDT) |I disagree with this, too. The problem (or blessing) is that people don't |want to write in assembly language, and the hardware which executes all those |complex (CISC) machine instructions is a waste of on-chip real-estate. |Typical C compilers only utilize a tiny fraction of the instructions available |on a CISC processor, so what's the point? The upshot of RISC is that these |chips are smaller, they require less power, they are more easily scaled down, |and less hardware is necessary for decoding the instructions, all of these |factors leading to much greater performance. The typical RISC microprocessor |contains under 100,000 transistor components. Compare that to the 1 million+ |in the 486! The only disadvantage I see with RISC is that executable programs |compiled for RISC are approximately 30% larger than equivalent programs |compiled for CISC. The reason the i486 has 1,000,000 transistors is because it has everything built-in... 8K cache, MMU, FPU, as will as the CPU itself and logic to handle the interactions within the chip. RISC itself is now even becoming a misnomer, because some RISC chips have more instruction that CISC chips, it's now Simple Instruction Set Chip (SISC)... The point is becoming moot as well, both CISC and RISC are merging and the most inportant think is to keep the instruction time to near 1 cycle or less. The '040 has an average cycle time of 1.3 and the instructions that do more (complex instruct.) take longer and the simpler ones shorter. whitewolf@gnh-starport!info-apple