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From: rhyde@gibson.ucr.edu (randy hyde)
Newsgroups: comp.sys.apple2
Subject: Re: HLLs vs. Assembly
Message-ID: <13497@ucrmath.ucr.edu>
Date: 10 Apr 91 17:56:20 GMT
References: <15682@smoke.brl.mil> <13275@ucrmath.ucr.edu> <1991Apr4.185435.28753@midway.uchicago.edu> <13347@ucrmath.ucr.edu> <1036@stewart.UUCP>
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Reply-To: rhyde@gibson.ucr.edu (randy hyde)
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RE: CISC vs. RISC

Yeah, RISCs are smaller, so what?  Yes, todays RISC chips use 100K xstrs, CISCs
use millions.  So what?  You can buy a 486 chip for less money than most RISC
chips.  Where is the savings?  CISC manufacturers are not standing still, they
are using those extra transistors to eliminate microcode in the frequently
executed instructions (on a 386 or 486, for example, the LOOP instruction is
actually *slower* than the corresponding DEC CX, JNE instructions because the
DEC and JNE instructions are implemented via random logic and the LOOP
instruction is microcoded; in a future version of the 80x86 family we'll
probably see *all* of the instructions implemented in random logic.  It
just takes time to do this).

>>> All of these factors lead to increased performance.

Then why are CISC processors like the 80486 and 68040 comparing
favorably or even out-performing their RISC competitors at equivalent
clock speeds.  As for the "They can run at faster clock speeds
arguement",  CISC is only about a year behind in brute force clock
speeds, in terms of system throughput rates, high end CISC compares
favorably against high-end RISC today.

RISC has had the obvious benefit of making CISC producers stand up and
take notice.  They've stopped using microcode so much and they're
switching to the use of random logic for instruction decoding (*exactly*
the hardware equivalent of the assembly language vs. C arguement).