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From: grue@cs.uq.oz.au (Frobozz)
Newsgroups: comp.sys.handhelds
Subject: Request for timing info for Saturn processor
Message-ID: <723@uqcspe.cs.uq.oz.au>
Date: 11 Apr 91 03:36:15 GMT
Sender: news@cs.uq.oz.au
Reply-To: grue@cs.uq.oz.au
Organization: Computer Science Department, The University of Queensland, Brisbane, Australia
Lines: 53


hiya,
	I'm writing a small (??) program for the 48 and I would like to know
some details about the timing of some of the instructions available (I don't
have the tech doc for the Saturn processor).  I particular, I would like to
know the timings of the following (using Alonzo's notation):

81A?0?	Move.? a/c, r?
81A?1?	Move.? r?, a/c
81A?2?	Swap.? a/c, r?
10?	Move.w a/c, r?
11?	Move.w r?, a/c
12?	Swap.w a/c, r?
BF?	Srn.w reg	? = [4,5,6,7]
81?	Rrn.w reg	? = [4,5,6,7]

These are the move from either a or c into one of the temporary registers for
the various different fields.  (I really like the way that you can specify the
.w field in 2 different instructions).

Also the following would also be helpful:

13?	swap.a	a/c, d?
14?	move.a	?, ?	indirect memory references
16?	add.a	?+1, d0
18?	sub.a	?+1, d0

These are the shift/rotate right by nibble instructions.


My problem is that I am going to require more data space that there are
registers in the processor.  Due to the limited ranges of the data that
is going to be kept around, I would be able to stuff more than one item
into each CPU register (who really needs 64 bits anyway).  I was wondering
what the performance hit would be like to use the shift/rotate instructions
to grab bits out of the registers as well as the cost of transfering stuff
from the temp registers to the cpu registers.  The alternative to over using
the CPU registers is to define an area of memory and indirectly address that
(I won't be able to dedicate an address register to this task but I would be
able to cache the address in one of the temp registers).



        						Pauli
seeya

Paul Dale               | Internet/CSnet:            grue@cs.uq.oz.au
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