Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!thunder.mcrcim.mcgill.edu!panisset
From: panisset@thunder.mcrcim.mcgill.edu (Jean-Francois Panisset )
Newsgroups: comp.sys.m68k
Subject: HALT* on 68020 question
Summary: contradiction in documentation
Keywords: MC68020 HALT* input vs. input/output
Message-ID: <1991Apr11.183130.24243@thunder.mcrcim.mcgill.edu>
Date: 11 Apr 91 18:31:30 GMT
Organization: McGill Research Centre for Intelligent Machines
Lines: 33

I have the MC68020 Third edition documentation (is there a newer one?),
and I have found what appears to be conflicting information about
the HALT* signal. In section 5.9.2, the signal is descibed in the following
way:

"The halt signal indicates that the processor should suspend bus activity or,
when used with BERR*, that the processor should retry the current cycle.
Refer to 7.5 BUS EXCEPTION CONTROL CYCLES for a description of the effects
of HALT* on bus operations."

And in section 5.13, the Signal Summary, HALT* is listed as an input signal.

But in section 7.5.4, "Double Bus Fault", the last line of the first
paragraph reads:
"When a double bus fault occurs, the processor halts and drives the HALT*
line low".

So what is going on? Is HALT* input only or is it input/output? And if
it is input/output, is it an open-collector output?

On a related note, I am interfacing the 68020 to the VTC VIC068 VME ASIC.
Due to the configuration of the ASIC, it is simpler if the HALT* line is
driven low at the same time as the RESET* line is driven low when the
68020 is to be reset. Does this cause a problem? Should I prevent this
from happening?

Thanks in advance to all you 68k gurus out there...

JF



-- 
Jean-Francois Panisset                    
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