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From: robertb@june.cs.washington.edu (Robert Bedichek)
Newsgroups: comp.sys.m88k
Subject: Re: Exception handling in the 88's
Message-ID: <1991Apr10.173352.28379@beaver.cs.washington.edu>
Date: 10 Apr 91 17:33:52 GMT
References: <28961@dime.cs.umass.edu> <2524@urbana.mcd.mot.com>
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Organization: Computer Science & Engineering, U. of Washington, Seattle
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In article <2524@urbana.mcd.mot.com> aduane@urbana.mcd.mot.com (Andrew Duane) writes:
>In article <28961@dime.cs.umass.edu> black@par1.cs.umass.edu.CS.UMASS.EDU (David K. Black) writes:
>>
>>In the MC88100 User's manual on pages 6-8 and 6-9 (Section 6.4.2)
>>there apears a discussion of two methods for exception processing
>>in the 88's.  To summarize:
>
>>Method 1: Disable interrupts etc and don't save any context to memory.
>>Use the rte instruction to restore control registers.  Shadowing remains
>>disabled and a non-trap exception will crash the machine.
>
>>My question is: Under what cicumstances is the first method acceptable?
>>Are there any OS code writers within "the sound of my voice" who have 
>>actually confronted this problem?
>
>I have seen some of the responses to this so far, and thought that it
>would be appropriate for me to cast the single "yes" vote.
>
>I am doing interrupt and other locore work for the motorola MVME188QP
>quad processor board. We have designed a set of "fast" interrupts that
>are propagated from processor to processor to do hardware operations
>such as updating the IEN enable masks. This requires no context to
>be saved, and was designed around being very fast for the interrupted
>processor, so we do it in about 20 instructions or so right at interrupt
>time, before any saving or re-shadowing is done. At RTE from this, any
>other pending exceptions will he handled normally.

As Andrew Klossner pointed out, you do have to check for faulted
transactions in the DMU and handle them.  You could run for a while
without doing this and not notice because for the bug to show up you
would have to have one of your "fast" interrupts happen just when the
interrupted processor was taking a page fault.

Btw, I plan to use method #1 in an multiprocessor project that we are
working on here at UW.  Exceptions on the 88k don't have to be piggy if
one doesn't mind keeping the FPU off and staying in assembly code and
not being able to field interrupts (or any other exception) during the
handler.

	Robert Bedichek    robertb@cs.washington.edu