Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!cs.utexas.edu!sun-barr!newstop!sun!amdcad!sono!miklg
From: miklg@sono.uucp (Michael Goldman )
Newsgroups: comp.arch
Subject: Re: Mass produced custom chips
Message-ID: <1991Apr15.154955.2452@sono.uucp>
Date: 15 Apr 91 15:49:55 GMT
References: <3329@crdos1.crd.ge.COM>
Organization: Acuson; Mountain View, California
Lines: 22

Bill Davidsen suggested a custom CPU as a chip for the future.

 I read about, and got some literature, on a chip from Phillips
which is a programmable gate array with a programming time on the
order of ~1 ms.  Their idea is that people would put their code
into boolean, and *swap* it in and out of the gate array with
the process - e.g., it could be TCP/IP code one time slice and
X.25 code the next.  It's still fairly new, and the idea seems
exciting, but possibly ahead of its time.  It would be nice if
it really caught on, and we could get away from this concept of
a single CPU with registers, and simply have our algorithms re-
designed by the compiler to take advantage of the generality and
parallelism inherent in general logic.  We could have a number of
different architectures for the gate arrays, with our compiler trans-
lating our code into Boolean, with the manufacturer's utility 
translating that into the particular architecture of their gate
array.  There are a lot of applications that would benfit from
parallelism - matrix multiplication, searching, numerical integration,
etc.

I'm afraid without a certain momentum from a number of big users it
won't catch on, but maybe !?