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From: sweany@berlioz.cs.colostate.EDU (Phil Sweany)
Newsgroups: comp.arch
Subject: Re: Instruction Scheduling
Message-ID: <14254@ccncsu.ColoState.EDU>
Date: 15 Apr 91 21:21:59 GMT
References: <32097@shamash.cdc.com> <1991Apr8.224717.14402@aero.org> <PAULB.91Apr11130041@rcx1.ssd.csd.harris.com>
Sender: news@ccncsu.ColoState.EDU
Reply-To: sweany@berlioz.cs.colostate.EDU (Phil Sweany)
Organization: Colorado State University
Lines: 41

In article  <MEISSNER.91Apr11114114@curley.osf.org> 
   meissner@osf.org (Michael Meissner) writes :

} However at the assembly level can be too late if the latency is high
} enough.

(and continues with an example where reusing a hard register will limit
 instruction scheduling due to a reuse of a register, leading to an
 anti-dependency on that register).


In article <PAULB.91Apr11130041@rcx1.ssd.csd.harris.com> 
  paulb@ssd.csd.harris.com  (Paul Beusterien) suggests

  > This example shows the value of a register reallocator that happens
  > as a pre-pass to instruction scheduling.  


Another (better ?) solution is available if graph coloring register 
assginment is used.  Since the problem is caused by anti-dependencies
on the hard registers which limit scheduling's ability to overlap
operations, we can circumvent it by delaying the assignment
of symbolic registers until after instruction scheduling has taken place.
Steve Beaty and I described such a scheme in: 

@inproceedings
{
        SwBe90,
        topic =         confp,
        author =        "Sweany, P. and Beaty, S.",
        title =         "Post-Compaction Register Assignment in a
				Retargetable Compiler",
        booktitle =     "Proceedings of the 23th Microprogramming
				Workshop (MICRO-23)",
        address =       "Orlando, FL",
        month =         "November",
        year =          "1990"
}

---
Phil Sweany			sweany@cs.colostate.edu