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From: sysmgr@KING.ENG.UMD.EDU (Doug Mohney)
Newsgroups: comp.arch
Subject: Re: Re: Snakebytes (HP process technology)
Message-ID: <00947104.8B2D8080@KING.ENG.UMD.EDU>
Date: 13 Apr 91 14:41:28 GMT
References: <40812@cup.portal.com>,<32580016@hpcuhe.cup.hp.com>
Sender: news@eng.umd.edu (C-News)
Reply-To: sysmgr@KING.ENG.UMD.EDU (Doug Mohney)
Organization: The U. of MD, CP, CAD lab
Lines: 27

In article <32580016@hpcuhe.cup.hp.com>, linley@hpcuhe.cup.hp.com (Linley Gwennap) writes:
>  While HP's IC
>fabrication processes are very good, they are not out on the "bleeding
>edge", so there's plenty of room for future improvement.  (For bleeding
>edge, try TI's 0.8 micron BiCMOS process!)

Can you (without lotta headaches) put HP-PA on Gallium Arsenide <sp>?

>To clarify another inquiry, of the three large chips (CPU, FPU, MC) in
>the Series 700, two are fabbed by HP.  The FPU is fabbed by TI in a 0.8
>micron, two metal-layer CMOS process. 

So the TI floating-point goodie is the most expensive chip sitting in your box,
due to the fabrication process, among other things? (TI: Good, but pricy) Could
you offer a Real Cheap Snake (snakette?) with a goal of 20MIPS/5K given the
current technology? 

> While Hitachi is not involved in the Series 700, they have licensed the 
>PA-RISC architecture and are
>expected to produce PA-RISC chips in the future.

Will they be offering complementary low-end machines to the Snake? Have any
other companies considered licensing PA-RISC? 


     Signature envy: quality of some people to put 24+ lines in their .sigs
  -- >                  SYSMGR@CADLAB.ENG.UMD.EDU                        < --