Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!elroy.jpl.nasa.gov!decwrl!waikato.ac.nz!ldo
From: ldo@waikato.ac.nz (Lawrence D'Oliveiro, Waikato University)
Newsgroups: comp.arch
Subject: Re: Loop instructions
Message-ID: <1991Apr16.152438.3445@waikato.ac.nz>
Date: 16 Apr 91 03:24:38 GMT
References: <1991Apr15.193425.3436@waikato.ac.nz> <2302@spim.mips.COM>
Organization: University of Waikato, Hamilton, New Zealand
Lines: 27

On the 68000 family, the DBcc loop instructions decrement the 16-bit count
register and stop looping when it reaches -1 (or 65535), not 0. To compensate
for this, you do *not* subtract one from the initial loop count. Instead,
you enter the loop by branching to the DBcc at its end, rather than by
falling in the top. Thus, here's an example sequence to copy a block
of bytes:

	; get source pointer into a0
	; get destination pointer into a1
	; get 16-bit count into d0
		bra.s	@2		; enter loop at end
	@1	move.b	(a0)+, (a1)+
	@2	dbra	d0, @1

The idea behind this is, if the loop count is initially zero, the
DBcc will fall through without executing the loop at all--no need for
a separate test.

I just wondered if other CPU designers thought this was a neat concept
as well, or whether they tended to go for the "decrement-until-zero"
brand of loop instruction.

Lawrence D'Oliveiro                       fone: +64-71-562-889
Computer Services Dept                     fax: +64-71-384-066
University of Waikato            electric mail: ldo@waikato.ac.nz
Hamilton, New Zealand    37^ 47' 26" S, 175^ 19' 7" E, GMT+12:00
"[Word processing and spreadsheets] aren't very interesting to me." -- Bill Joy