Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!bu.edu!m2c!seqp4!jdarcy
From: jdarcy@seqp4.ORG (Jeff d'Arcy)
Newsgroups: comp.arch
Subject: Re: Bitfield instructions--a good idea?
Message-ID: <712@seqp4.UUCP>
Date: 15 Apr 91 13:54:47 GMT
References: <1991Apr15.193425.3436@waikato.ac.nz>
Organization: Sequoia Systems, Marlboro MA
Lines: 25

ldo@waikato.ac.nz (Lawrence D'Oliveiro, Waikato University) writes:
>What do RISC designers think of bitfield instructions? (A la
>the VAX and 680x0 [x >= 2] processors: extract so many bits at
>a certain offset, insert so many bits at a certain offset, etc.)

I'm not a RISC designer, but I play one on TV.  Oops.  Seriously, I think
the RISC designers out there would be fools not to understand the value of
making their chips pleasant for low-level OS geeks (like me) to use, so
here are my two bits.

My experience with bitfield instructions is with the Moto 88K, which I think
uses them in a very elegant fashion.  The 88K has *no* shift instructions
(it does have rotate), using the make, extract, and extract unsigned bitfield
instructions for left shift, arithmetic and logical right shift respectively.
These execute in one cycle apiece like all other integer instructions and
provide a very intuitive superset of the shift instructions.

I found these instructions particularly useful when I was doing instruction
emulation in my last OS's exception handlers; they allowed me to play with
instruction fields directly instead of having to do all sorts of annoying
shift-and-mask operations.
-- 

  Jeff d'Arcy, Generic MTS, Sequoia Systems Inc. <jdarcy%seqp4@m2c.org>
Yonder nor sorghum stenches shut ladle gulls stopper torque wet strainers