Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!swrinde!elroy.jpl.nasa.gov!decwrl!fernwood!portal!cup.portal.com!mslater From: mslater@cup.portal.com (Michael Z Slater) Newsgroups: comp.arch Subject: Re: Bitfield instructions--a good idea? Message-ID: <41329@cup.portal.com> Date: 16 Apr 91 14:56:59 GMT References: <1991Apr15.193425.3436@waikato.ac.nz> Organization: The Portal System (TM) Lines: 28 Michael Saleeba writes: >I rather like the Texas Instruments graphics processors' attitude to this >problem. All instructions are addressed by bit, irrespective of the maximum >physical word size, and most instructions (as far as I remember) allow a >nice range of bitfield lengths for their operands. Surely this is a neater >way to design a system than to rely on combinations of arbitrary byte and >word boundaries. > >It could be argued that this would lead to a conflict with the basic goals of >RISC design and general inefficiency. I suppose the best comment here is that >the TMS34010 and TMS34020 are quite RISCy, and are also pretty damn fast; >mainly through exploiting RISC design goals. I don't think the 340x0 can be called "quite RISCy" in any meaningful sense of the term. They have a load/store architecture, but the aren't heavily pipelined (each instruction takes 4 clocks on a 34020, 8 clocks on a 34010) and use microcode. They have complex addressing modes and variable-length instructions. As for "pretty damn fast", the 40-MHz 34020 executes at a PEAK rate of 10 NATIVE MIPS. It may be fast in some applications, but this comes from its CISCyness -- the fact that it has complex instructions that are well- suited to some applications, notably graphics. As for RISCs with bit-field operations, both the 88000 and HP-PA have them. Michael Slater, Microprocessor Report mslater@cup.portal.com