Newsgroups: comp.arch
Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!wuarchive!rice!ariel.rice.edu!preston
From: preston@ariel.rice.edu (Preston Briggs)
Subject: Re: Instruction Scheduling
Message-ID: <1991Apr17.063936.18603@rice.edu>
Sender: news@rice.edu (News)
Organization: Rice University, Houston
Date: Wed, 17 Apr 91 06:39:36 GMT

cs450a03@uc780.umd.edu writes:

>Are there any architectures with setbranch/commit semantics?  (where
>setbranch sets up a branch target, and allows for pipeline stuffing,
>and commit actually changes flow of control).

The proposed Tera machine has 8 _target registers_ that can serve
as the target of branches.  I don't know what they'll actually do when
the machine is built.  In addition to preloading some of the pipeline
in each direction, others have proposed prefetching and locking the
appropriate I-cache and TLB lines.

Preston Briggs