Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!crdgw1!crdos1!davidsen From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) Newsgroups: comp.arch Subject: Re: overview of HP-PA Bitfield insts. Message-ID: <3354@crdos1.crd.ge.COM> Date: 17 Apr 91 13:13:18 GMT References: <1991Apr15.193425.3436@waikato.ac.nz> <51584@apple.Apple.COM> <1991Apr17.180036.3459@waikato.ac.nz> Reply-To: davidsen@crdos1.crd.ge.com (bill davidsen) Organization: GE Corp R&D Center, Schenectady NY Lines: 23 In article <1991Apr17.180036.3459@waikato.ac.nz> ldo@waikato.ac.nz (Lawrence D'Oliveiro, Waikato University) writes: | The only way I can see around this is to update the width value in | the instruction itself--using self-modifying code. Hmmm, I seem to | recall from another discussion some time ago that the HP-PA is one | of those processors that will correctly invalidate its instruction cache | if you do any writes to program code in memory. So this should work | quite nicely. Excuse me while I call Ralph on the porcelain intercom... this is a good argument for an "execute" instruction, allowing you to build the instruction in a register (hopefully) or the stack (if you must) and then force an instruction fetch on it. No matter how you do it you will slow things down to the point where it's unlikely to be faster than the mask and shift, unfortunatly. I like the bitfield instructions in the 32x32 series, which really has an orthogonal register set, rather than general and arithmetic registers. -- bill davidsen (davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen) "Most of the VAX instructions are in microcode, but halt and no-op are in hardware for efficiency"