Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!elroy.jpl.nasa.gov!david
From: david@elroy.jpl.nasa.gov (David Robinson)
Newsgroups: comp.arch
Subject: SPARC implementation or architecture
Message-ID: <1991Apr17.183822.7681@elroy.jpl.nasa.gov>
Date: 17 Apr 91 18:38:22 GMT
Sender: david@elroy.jpl.nasa.gov (David Robinson)
Organization: Image Analysis Systems Group, JPL
Lines: 31

[I hope this doesn't start any religious wars about which RISC is "better"]

In looking at the various RISC chips that are on the market and the
various integer benchmarks, it appears that all of the SPARC based
machines have a lower rating for an equivilant clock speed.  I know that
something like SPECint/Mhz is not a great measure of worth but it
does pose a couple questions. 

Most of the RISC chips (MIPS, HP-PA, RS6000) seem to be having a 
SPECint/Mhz ratio of 0.70 - 0.80 while the SPARC systems come
in around 0.50.  From a buyer point of view, if
I can buy a 20 SPECint machine for $10K then I don't care if it
has an internal clock of 10Mhz or 100Mhz.  But from an architecture
point of view I want to know why one chip out performs another at
the same clock speed.  Is it an implementation issue such as the
fab process used effecting gate delays, or the design process
such as complete custom vs cell libraries, or design trade offs
such as pipeline depth?  If not an implementation issue then is
it a fundimental architecture issue such as lack of integer
multiply and divide or register windows vs large flat register file.

Has anyone compared why SPARC tends to run slower at the same clock
speed as other RISC chips?  Will this be a factor as the clock rate
is cranked up to 100Mhz and beyond?

	-David
-- 
David Robinson	david@elroy.jpl.nasa.gov 	{decwrl,usc,ames}!elroy!david
Disclaimer: No one listens to me anyway!
"Once a new technology rolls over you, if you're not part of the steamroller,
 you're part of the road." - Stewart Brand